Semiconductor device and method of manufacturing same

ABSTRACT

To provide a semiconductor device having improved reliability. 
     In a wiring board of BGA, an insulation layer has thereon a plurality of bonding leads. The insulation layer is comprised of a prepreg having a glass cloth and a resin layer not having the glass cloth. The prepreg has thereon the resin layer. The bonding leads are arranged directly on the soft resin layer and are therefore supported by this soft resin layer. When a load is applied to each of the bonding leads during flip chip bonding, the resin layer sinks, by which a stress applied to a semiconductor chip can be relaxed.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2013-086899 filed onApr. 17, 2013 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor device and a technologyof manufacturing same, for example, a technology effective when appliedto a semiconductor device obtained by mounting a semiconductor chip on awiring board by using a flip chip bonding technology.

Japanese Patent Laid-Open No. 2004-165311 (Patent Document 1) describesa structure in which a semiconductor chip is connected with a pad on achip mounting surface of a board via a metal post.

Japanese Patent Laid-Open No. 2007-329396 (Patent Document 2) describesa structure in which a semiconductor substrate is arranged on a mountboard via a metal column and a protruding electrode arranged at the endthereof.

Japanese Patent Laid-Open No. 2009-289908 (Patent Document 3) describesa structure in which electrical connection between the pad of asemiconductor chip and the bonding lead of a wiring board is achieved bygold-solder bonding between a solder formed on a bonding lead and a bumpelectrode made of gold.

-   [Patent Document 1] Japanese Patent Laid-Open No. 2004-165311-   [Patent Document 2] Japanese Patent Laid-Open No. 2007-329396-   [Patent Document 3] Japanese Patent Laid-Open No. 2009-289908 (FIGS.    38 and 39)

SUMMARY

In flip chip bonding technology, a semiconductor chip is mounted on awiring board via a columnar (post-like or pillared) conductive member,for example, as described above in Patent Documents 1 and 2 or asemiconductor chip is mounted on a wiring board via a protruding(bump-like) conductive member as described above in Patent Document 3.In flip chip bonding technology, when a semiconductor chip is mounted, aload is applied to the semiconductor chip arranged on a wiring board ina direction perpendicular thereto (in a thickness direction of thewiring board).

There are however variations among electrodes (bonding leads, electrodeswith which a conductive member is connected) formed on a chip mountingsurface of a wiring board, columnar (post-like) or protruding(bump-like) conductive members to be used for electrically connecting asemiconductor chip with a wiring board, or both the electrodes and theconductive members.

In other words, respective surfaces (surfaces with which conductivemembers are connected) of electrodes do not always have the same height(in other words, are not always flush with each other) or conductivemembers do not always have the same height (size) (in other words, arenot always flush with each other) due to an influence of variations inprocessing. When a semiconductor chip is arranged on a wiring board,some of the conductive members fail to contact with the electrodes ofthe wiring board.

When an insulation layer (an insulation layer with which electrodes comeinto contact) that supports the electrodes of a wiring board is not aprepreg (a resin layer containing a glass cloth), in other words, iscomposed of a resin layer not containing a glass cloth (which may alsobe called “glass fibers”), the insulation layer has hardness (rigidityor strength) lower than that of the prepreg.

As shown in FIG. 25, application of a load to a semiconductor chip 50sinks a bonding lead 64 of a wiring board 60 with which a bump 52, aconductive member, comes into contact. In other words, application of aload to a resin layer 61 not containing a glass cloth causes deformationof this resin layer 61.

Even if bumps 52 or bonding leads 64 vary in height, this variation inheight can be absorbed by sinking of the bonding leads 64 so that abonding failure between the bumps 52 and the bonding leads 64 can besuppressed.

As described above, on the other hand, the resin layer 61 not containinga glass cloth has a hardness lower than that of a resin layer 66(prepreg) containing a glass cloth 65 which layer is shown in FIG. 26. Asemiconductor device not using a prepreg as a resin layer that supportsa wiring layer including the bonding leads 64 is disadvantageous fromthe standpoint of thinning a semiconductor device.

When the resin layer (prepreg) 66 is employed as an insulation layerthat supports electrodes such as bonding leads 64 as shown in FIG. 26,however, it does not easily deform different from the resin layer 61 notcontaining a glass cloth even if a load is applied to this resin layer66. The bonding leads 64 formed on this resin layer 66 therefore do notsink. In other words, since the resin layer 66 which is an insulationlayer does not easily deform, it is difficult to absorb variations inheight among the bumps or bonding leads.

An object of an embodiment disclosed herein is to provide a technologycapable of improving the reliability of a semiconductor device.

Other objects and novel features will be apparent from the descriptionherein and accompanying drawings.

A semiconductor device according to one embodiment includes a wiringboard having a first insulation layer, a plurality of bonding leads, anda plurality of lands and a semiconductor chip mounted on the wiringboard via a plurality of conductive members such that the main surfaceof the semiconductor chip faces to the wiring board. The conductivemembers are connected with the bonding leads of the wiring board via aplurality of solder materials, respectively. In the above-mentionedsemiconductor device, the first insulation layer is comprised of a firstresin layer having glass fibers and a second resin layer having no glassfibers and each of the bonding leads is in contact with the second resinlayer.

According to the above-mentioned one embodiment, a semiconductor devicehaving improved reliability can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view showing one example of the structure of asemiconductor device according to the embodiment;

FIG. 2 is a cross-sectional view showing one example of the structuretaken along a line A-A shown in FIG. 1;

FIG. 3 is a back surface view showing one example of the back surfaceside structure of the semiconductor device shown in FIG. 1;

FIG. 4 is a plan view showing one example of the upper surface sidestructure of a wiring board to be incorporated in the semiconductordevice shown in FIG. 1;

FIG. 5 is a cross-sectional view showing one example of the structuretaken along a line A-A shown in FIG. 4;

FIG. 6 is an enlarged fragmentary cross-sectional view showing oneexample of the structure of portion B shown in FIG. 5;

FIG. 7 is a back surface view showing one example of the lower surfaceside structure of the wiring board shown in FIG. 4;

FIG. 8 is a plan view showing one example of the main surface sidestructure of a semiconductor chip to be mounted on the semiconductordevice shown in FIG. 1;

FIG. 9 is a cross-sectional view showing one example of the structuretaken along a line A-A shown in FIG. 8;

FIG. 10 is a back surface view showing one example of the back surfaceside structure of the semiconductor chip to be mounted on thesemiconductor device shown in FIG. 1;

FIG. 11 is a cross-sectional view showing one example of the structuretaken along a line A-A of FIG. 10;

FIG. 12 is a plan view showing one example of the structure of a wiringboard to be used in the fabrication of the semiconductor device shown inFIG. 1;

FIG. 13 is a cross-sectional view showing one example of the structuretaken along a line A-A of FIG. 12;

FIG. 14 is a cross-sectional view showing one example of the structureof one device region in the wiring board shown in FIG. 12;

FIG. 15 is a cross-sectional view showing one example of the structureafter solder precoating in the fabrication of the semiconductor deviceshown in FIG. 1;

FIG. 16 is a plan view showing one example of the structure afterunderfill application in the fabrication of the semiconductor deviceshown in FIG. 1;

FIG. 17 is a cross-sectional view showing one example of the structuretaken along a line A-A in FIG. 16;

FIG. 18 is a cross-sectional view showing one example of the structureafter chip mounting in a flip chip bonding step in the fabrication ofthe semiconductor device shown in FIG. 1;

FIG. 19 is a cross-sectional view showing one example of the structureafter pressure bonding of the chip in the flip chip bonding step shownin FIG. 18;

FIG. 20 is a cross-sectional view showing one example of the structureafter ball mounting in the fabrication of the semiconductor device shownin FIG. 1;

FIG. 21 is a plan view showing one example of lead arrangement on theupper surface side of a wiring board to be incorporated in asemiconductor device according to Modification Example 1 of theembodiment;

FIG. 22 is a cross-sectional view showing one example of the structureof a semiconductor device according to Modification Example 2 of theembodiment;

FIG. 23 is a cross-sectional view showing one example of the structureof a wiring board to be incorporated in a semiconductor device accordingto Modification Example 4 of the embodiment;

FIG. 24 is an enlarged fragmentary cross-sectional view showing oneexample of a wiring board of Modification Example 5 of the embodiment;

FIG. 25 is an enlarged fragmentary cross-sectional view showing a firststructure during load application in flip chip bonding investigated bythe present inventors; and

FIG. 26 is an enlarged fragmentary cross-sectional view showing a secondstructure during load application in flip chip bonding investigated bythe present inventors.

DETAILED DESCRIPTION

In the below-described embodiment, descriptions on the same or likeparts will essentially be omitted unless particularly necessary.

In the below-described embodiment, a description will be made afterdivided in plural sections or in plural embodiments if necessary forconvenience sake. These plural sections or embodiments are notindependent each other, but in a relation such that one is amodification example, details, or complementary description of a part orwhole of the other one unless otherwise specifically indicated.

In the below-described embodiment, when a reference is made to thenumber of elements (including the number, value, amount, range, and thelike), the number of elements is not limited to a specific number butmay be greater than or less than the specific number unless otherwisespecifically indicated or in the case it is principally apparent thatthe number is limited to the specific number.

Moreover in the below-described embodiment, it is needless to say thatthe constituting elements (including element steps) are not alwaysessential unless otherwise specifically indicated or in the case whereit is principally apparent that they are essential.

In addition, it is needless to say that referring to constitutingelements used in the below-described embodiment, the term “is made ofA”, “is comprised of A”, “has A”, or “includes A” does not exclude theother elements unless otherwise specifically indicated that theconstituting element is limited to only the specific element. Similarly,in the below-described embodiment, when a reference is made to the shapeor positional relationship of the constituting elements, thatsubstantially analogous or similar to it is also embraced unlessotherwise specifically indicated or principally apparent that it is not.This also applies to the above-described value and range.

The embodiment of the invention will hereinafter be described in detailbased on the drawings. In all the drawings for describing theembodiment, members of a like function will be identified by likereference numerals and overlapping descriptions will be omitted.Further, to facilitate understanding of the drawings, even plan viewsmay be sometimes hatched.

Embodiment Semiconductor Device

FIG. 1 is a plan view showing one example of the structure of asemiconductor device according to the embodiment; FIG. 2 is across-sectional view showing one example of the structure taken along aline A-A shown in FIG. 1; and FIG. 3 is a back surface view showing oneexample of the back surface side structure of the semiconductor deviceshown in FIG. 1.

The constitution of the semiconductor device according to the embodimentshown in FIGS. 1 to 3 will next be described. As shown in FIG. 2, thesemiconductor device of the present embodiment has a wiring board 2. Asemiconductor chip 1 is flip-chip bonded onto this wiring board 2. Thismeans that the semiconductor chip 1 is mounted on an upper surface 2 aof the wiring board 2 via a plurality of conductive members such that amain surface 1 a of the semiconductor chip 1 faces to an upper surface(chip mounting surface) 2 a of the wiring board 2.

On the other hand, the wiring board 2 has, on a lower surface 2 bthereof, a plurality of solder balls 5 which will serve as externalterminals of the semiconductor device. In the present embodiment, thesesolder balls 5 are arranged in lattice form in a plan view as shown inFIG. 3.

Accordingly, in the present embodiment, a BGA (ball grid array) 7 willbe described as one example of the above-mentioned semiconductor device.

In the BGA 7 according to the present embodiment, a plurality of pads(electrodes) 1 c provided on the main surface (element formationsurface) la of the semiconductor chip 1 and a plurality of bonding leads(electrodes) 2 m provided on the upper surface 2 a of the wiring board 2are electrically connected with each other via conductive members andsolder materials (connection members) 3, respectively.

In the BGA 7 according to the present embodiment, the pads 1 c of thesemiconductor chip 1 have thereon the conductive members. In the presentembodiment, the BGA 7 using a copper (Cu) pillar 4 as the conductivemembers will be described. The copper pillars 4 are each made of amaterial composed mainly of copper and at the same time, they arecolumnar (post-like) electrodes. The semiconductor chip 1 is thereforeflip chip connected with the wiring board 2 via these copper pillars 4formed respectively on the surfaces of the pads 1 c on the main surface1 a of the semiconductor chip. In the flip chip bonding, the copperpillars 4 are electrically connected with the bonding leads 2 m of thewiring board 2, respectively, via the solder materials 3 respectivelyarranged on the end surfaces (surfaces opposite to the bonding leads 2m) of the copper pillars.

As the solder materials 3 described herein, so-called lead-free soldersubstantially free from lead (Pb) is preferred. It is, for example, atin-silver (Sn—Ag) solder.

Using such a material makes it possible to cope with an environmentalpollution problem. The term “lead-free solder” means a solder having acontent of lead (Pb) not greater than 0.1 wt %. This content has beendetermined as the standard of RoHS (restriction of hazardous substances)instruction.

In the BGA 7, on the side of the upper surface 2 a of the wiring board2, a space formed between the semiconductor chip 1 and the wiring board2 is filled with an underfill 6 which is a molding resin, as shown inFIG. 2. This underfill 6 is, for example, an epoxy resin and the spaceis filled with it so as to ensure connection reliability between thesemiconductor chip 1 and the wiring board 2.

The underfill 6 also covers the side surface of the semiconductor chip1. This makes it possible to protect a flip-chip connection (aconnection between the copper pillar 4 and the bonding lead 2 m) and inaddition, to prevent penetration of water from the outside (periphery)of the semiconductor chip 1 to the flip chip connection. A back surface1 b of the semiconductor chip 1 is however exposed, as shown in FIGS. 1and 2, while being directed toward the upper portion of the BGA 7.

The wiring board 2 is, as shown in FIG. 2, a multilayer wiring boardhaving a plurality of wiring layers. Described specifically, a corelayer 2 e has, on the surface and back surface thereof, a wiring layer 2i and a wiring layer 2 j and as shown in FIG. 5, an uppermost wiringlayer 2 p has the bonding leads 2 m for flip chip connection. On theother hand, a lowermost wiring layer 2 q has therein a plurality oflands (electrodes) 2 n for connecting therewith the solder ball(conductive member) 5 which is an external terminal of the BGA 7.

This means that the upper surface 2 a and the lower surface 2 b of thewiring board 2 have thereon solder resist films 2 c and 2 g, which areinsulation films, respectively. On the side of the upper surface 2 a,the solder resist film 2 c has, in an opening portion 2 k thereof, thebonding leads 2 m, while on the side of the lower surface 2 b, thesolder resist films 2 g have, in a plurality of opening portions 2 kthereof, lands 2 n, respectively.

In the wiring board 2 of the present embodiment, on the side of theupper surface 2 a, the bonding leads 2 m are arranged on an insulationlayer 2 d. This insulation layer 2 d is comprised of a prepreg (resinlayer) 2 da having a glass cloth (glass fibers) 2 h and a resin layer 2db not having the glass cloth 2 h. More specifically, the resin layer 2db is formed (stacked) on the prepreg 2 da (surface on the side of thesemiconductor chip 1).

Accordingly, each of the bonding leads 2 m contacts with the resin layer2 db and are arranged on this resin layer 2 db. Further, the bondingleads 2 m are connected with the copper pillars 4 via the soldermaterials 3, respectively, so that the prepreg 2 da and each of thecopper pillars 4 have therebetween the resin layer 2 db.

When the prepreg 2 da having the glass cloth 2 h and the resin layer 2db not having the glass cloth 2 h are compared, the prepreg 2 da hasgreater (higher) hardness and greater rigidity. This means that theprepreg 2 da having the glass cloth 2 h is hard, while the resin layer 2db not having the glass cloth 2 h is soft.

The each of bonding leads 2 m contacts with the soft resin layer 2 db(layer not containing a glass cloth) without having therebetween theprepreg 2 da containing the glass cloth (glass fibers) 2 h.

As described above, in the wiring board 2 of the BGA 7, the prepreg 2 dahave thereon the bonding leads 2 m via the soft resin layer 2 db so thatapplication of a load by flip chip connection or the like causesdeformation of the resin layer 2 db and sinking of the bonding leads 2m. Even if variations in height occur among the copper pillars 4, allthe copper pillars 4 can therefore be connected with the bonding leads 2m. In short, even the copper pillar 4 having a low height can beconnected with the bonding lead 2 m.

In addition, the bonding lead 2 m of the wiring board 2 connected with,among the copper pillars 4, a copper pillar having a height greater thanthat of the other copper pillars 4 sinks so that formation of a crack 67(refer to FIG. 26) in an insulation layer immediately below the pad 1 cof the semiconductor chip 1 on which this high copper pillar 4 is formedcan be suppressed. This makes it possible to improve the reliability ofthe BGA 7.

Further, even when a stress is applied to the solder balls 5 or the likeof the BGA 7, this stress can be relaxed with the soft resin layer 2 dband direct propagation of the damage to the flip chip connection can besuppressed.

Described specifically, since the soft resin layer 2 db is arrangedbelow the bonding leads 2 m with which the copper pillar 4 is connected,even a stress including a thermal stress applied to the solder balls 5is absorbed by the deformation of the soft resin layer 2 db to relax thestress and prevent direct propagation of the damage to the flip chipconnection or semiconductor chip 1.

As a result, occurrence of a connection failure at the flip chipconnection can be suppressed.

<Wiring Board>

FIG. 4 is a plan view showing one example of the upper surface sidestructure of a wiring board to be incorporated in the semiconductordevice shown in FIG. 1; FIG. 5 is a cross-sectional view showing oneexample of the structure taken along a line A-A shown in FIG. 4; FIG. 6is an enlarged fragmentary cross-sectional view showing one example ofthe structure of portion B shown in FIG. 5; and FIG. 7 is a back surfaceview showing one example of the lower surface side structure of thewiring board shown in FIG. 4.

A detailed structure of the wiring board 2 according to the presentembodiment will next be described.

The wiring board 2 is, as described above, a multilayer wiring board andin the present embodiment, a multilayer wiring board having four wiringlayers will be described as an example. The number of the wiring layersis however not limited to four.

The wiring board 2 has an upper surface 2 a having a square planar shapeas shown in FIG. 4 and a lower surface 2 b which is a mount surface or aback surface opposite to the upper surface 2

As shown in FIG. 4, the wiring board 2 has, on the upper surface 2 athereof, a plurality of bonding areas 2 m for flip chip connectionformed on the uppermost wiring layer. They are arranged in two rows, aninside row and an outside row, in an opening portion 2 k of a solderresist film 2 c shown in FIG. 5. The bonding leads of the inside row andthe outside row are arranged without overlapping with each other so thatthey correspond to pads arranged on the side of the chip in a zigzagmanner and are suited for multi-pin connection.

From the opening portion 2 k of the solder resist film 2 c having thebonding leads 2 m therein, a resin layer 2 db that supports thesebonding leads 2 m is also exposed.

As shown in FIG. 7, on the other hand, on the lower surface 2 b of thewiring board 2, a plurality of lands 2 n for solder ball connectionformed in the lowermost wiring layer is arranged in a plurality ofopening portions 2 k of a solder resist film 2 g shown in FIG. 5,respectively, and these lands 2 n are arranged in lattice form.

As shown in FIGS. 5 and 6, the wiring board 2 is formed by laminating acore layer (prepreg) 2 e, wiring layers 2 i and 2 j respectivelyarranged on the upper surface and the lower surface of the core layer 2e, insulation layers (insulating films) 2 d and 2 f, and wiring layers 2p and 2 q which are the uppermost layer and the lowermost layer,respectively. These members are laminated with each other by contactbonding by pressing. For example, members such as the core layer 2 e,the wiring layers 2 i and 2 j, the insulation layers 2 d and 2 f, andthe wiring layers 2 p and 2 q are sandwiched between flat plate-likesteel plates and pressed at high temperature under high pressure.

Therefore, depending on the position of a device region 2 u (refer toFIG. 12), there occur variations in height, particularly among wirings(including electrodes such as the bonding leads 2 m and the lands 2 n)formed on the outermost layers such as uppermost layer and the lowermostlayer.

The wiring board 2 according to the present embodiment has a structurehaving four wiring layers as shown in FIG. 6. It has, on the surface andthe back surface of the core layer 2 e thereof, the wiring layer 2 i andthe wiring layer 2 j, respectively and has a plurality of wirings(wiring patterns) in the uppermost wiring layer 2 p and the lowermostwiring layer 2 q via the insulation layer 2 d and the insulation layer 2f. A portion of each of the wirings formed in the uppermost wiring layer2 p constitutes the plurality of bonding leads (electrodes) 2 m for flipchip connection.

Due to the above-mentioned manufacturing method (contact bonding) of thewiring board, therefore, variations in height tend to occur among thebonding leads 2 m which are electrodes formed in the uppermost(outermost) wiring layer 2 p.

The wiring board 2 has, in the lowermost wiring layer (on the side ofthe lower surface 2 b) 2 q, thereof, a plurality of lands 2 n forconnecting solder balls 5 therewith. This means that a portion of eachof the wirings formed in the lowermost wiring layer 2 q constitutes aplurality of lands (electrodes) 2 n for connecting therewith the solderballs which are outer terminals.

In the wiring board 2, the plurality of bonding leads 2 m is formed onthe side of the upper surface 2 a and the plurality of lands 2 ncorresponding to the plurality of bonding leads 2 m is formed on theside of the lower surface 2 b. The bonding leads 2 m and the lands 2 ncorresponding to each other are electrically connected with each othervia inner wirings, through-hole wirings, or the like which are notillustrated.

The wiring board 2 has, on the upper surface 2 a and the lower surface 2b thereof, solder resist films 2 c and 2 g which are insulating films,respectively. On the side of the upper surface 2 a, the solder resistfilm 2 c has, in the opening portion 2 k thereof, the plurality ofbonding leads 2 m, while on the side of the lower surface 2 b, thesolder resist film 2 g has, in the plurality of opening portions 2 kthereof, the lands 2 n, respectively.

This means that on the side of the upper surface 2 a of the wiring board2, the insulation layer 2 d has, on the upper surface thereof, thesolder resist film (upper surface side protective film) 2 c so as toexpose the plurality of bonding leads 2 m, while on the side of thelower surface 2 b of the wiring board 2, the insulation layer 2 f has,on the lower surface thereof, the solder resist film (lower surface-sideprotective film) 2 g so as to expose the plurality of lands 2 n.

On the side of the upper surface 2 a, the insulation layer 2 d hasthereon the plurality of bonding leads 2 m. This insulation layer 2 d iscomprised of a prepreg (resin layer) 2 da having a glass cloth (glassfibers) 2 h and a resin layer 2 db not having a glass cloth 2 h and thisprepreg 2 da has thereon the resin layer 2 db.

These bonding leads 2 m are therefore each in contact with the resinlayer 2 db and they are arranged on this resin layer 2 db. In otherwords, these bonding leads 2 m are supported by the resin layer 2 db.

Also on the side of the lower surface 2 b, the insulation layer 2 f hasthereon the plurality of lands 2 n. This insulation layer 2 f iscomprised of a prepreg (resin layer) 2 fa having a glass cloth (glassfibers) 2 h and a resin layer 2 fb not having a glass cloth 2 h. Similarto the side of the upper surface 2 a, the each of lands 2 n contactswith the resin layer 2 fb and they are arranged on this resin layer 2fb. In other words, these lands 2 n are supported by the resin layer 2fb.

The above-mentioned resin layers (resin materials) 2 db and 2 fb aremade of, for example, an epoxy resin. The resin of the resin layers 2 dband 2 fb is a resin not having a glass cloth (glass fibers) 2 h, thoughhaving a plurality of fillers.

On the other hand, the prepregs 2 da and 2 fa are made of, for example,an epoxy resin. The resin of the prepregs 2 da and 2 fa has a pluralityof fillers and further has a glass cloth (glass fibers) 2 h.

When the prepregs 2 da and 2 fa having a glass cloth 2 h and the resinlayers 2 db and 2 fb not having a glass cloth 2 h are compared, theprepregs 2 da and 2 fa have greater (higher) hardness and greaterrigidity. In other words, the prepregs 2 da and 2 ft having a glasscloth 2 h are hard, but the resin layers 2 db and 2 fb not having aglass cloth 2 h have small (low) hardness and are soft.

The bonding leads 2 m are each arranged directly on the soft resin layer2 db and this soft resin layer 2 db has therebelow the hard prepreg 2da.

On the other hand, the lands 2 n on the side of the lower surface 2 bare each arranged directly on the soft resin layer 2 fb and this softresin layer 2 fb has therebelow (on the side of the core layer 2 e, onthe side of the lower surface 2 b) the hard prepreg 2 fa.

The bonding leads 2 m, the lands 2 n, and wirings of the wiring layersin the wiring board 2 are each made of a material composed mainly ofcopper and the bonding leads 2 m and the lands 2 n have a platedsurface.

With regards to the thickness of each of the layers of the wiring board2, the prepregs 2 da and 2 fa which are resin layers have a thicknessof, for example, 30 μm and the resin layers 2 db and 2 fb on the prepreg2 da and 2 fa have a thickness of, for example, 5 μm. The core layer 2 ehas a thickness of, for example, from 40 to 60 μm and the wiring layerseach has a thickness of, for example, ten and several μm. This meansthat the resin layers 2 db and 2 fb are thinner than the prepregs 2 daand 2 fa.

The thickness of the resin layer 2 db may be equal to that of theprepreg 2 da or may be greater than that of the prepreg 2 da.

It is however preferred to make the resin layer 2 db or 2 fb thinnerthan the prepreg 2 da or 2 fa as in the present embodiment when thewarpage of the wiring board or thinning of the semiconductor device istaken into consideration.

The bonding leads 2 m of the wiring board 2 may have, on the surfacethereof, a solder material 3. The solder material 3 arranged on each ofthe copper pillars 4 and each of the bonding leads 2 m can absorbvariations in height of the members when a load is applied during flipchip connection.

When the solder material 3 is not arranged on each of the bonding leads2 m (the bonding leads 2 m made of solid copper or the bonding leads 2 mhaving a gold-plated surface), the cost of the BGA 7 can be reducedbecause the solder material 3 is not used.

<Semiconductor Chip>

FIG. 8 is a plan view showing one example of the main surface sidestructure of a semiconductor chip to be mounted on the semiconductordevice shown in FIG. 1; FIG. 9 is a cross-sectional view showing oneexample of the structure taken along a line A-A shown in FIG. 8; FIG. 10is a back surface view showing one example of the back surface sidestructure of the semiconductor chip to be mounted on the semiconductordevice shown in FIG. 1; and FIG. 11 is a cross-sectional view showingone example of the structure taken along a line A-A of FIG. 10.

As shown in FIGS. 8 and 9, the semiconductor chip has, on the mainsurface 1 a thereof, a plurality of pads 1 c in two rows at theperiphery (outer circumferential portion) of the main surface 1 a. Thesemiconductor chip 1 according to the present embodiment is suited formulti-pin connection so that these pads 1 c are provided in a zigzagmanner.

Further, as shown in FIGS. 10 and 11, the copper pillar 4, which areconductive members, are connected with the pads 1 c, respectively. Thecopper pillars 4 are each a columnar (post-like) electrode and made of,for example, a material having copper (Cu) as a main component.

The copper pillar 4 is formed, for example, by electroplating. Describedspecifically, this pillar is formed by placing, on the main surface(element formation surface) of an unillustrated semiconductor wafer, adry film having a plurality of round holes corresponding to the padarrangement in each of chip formation regions of the semiconductor waferand stacking in the holes from below by electroplating.

As the conductive member, a protruding (bump) electrode may be used. Theprotruding electrode is made of, for example, a material having gold(Au) as a main component. The protruding electrode is formed using awire bonding technology with a capillary so that a semiconductor waferis cut into semiconductor chips prior to the formation of thisprotruding electrode.

The columnar electrode is obtained by, as described above, forming a dryfilm (resist film) on the main surface of a semiconductor wafer and thenforming a plurality of pads of each of the chip formation regions, forexample, by electroplating (electroless plating can also be used). Fromthe standpoint of the number of steps for forming the conductive member,using a columnar (post-like) electrode is preferred as in the presentembodiment.

<Manufacturing Method of Semiconductor Device>

FIG. 12 is a plan view showing one example of the structure of a wiringboard to be used in the fabrication of the semiconductor device shown inFIG. 1; FIG. 13 is a cross-sectional view showing one example of thestructure taken along a line A-A of FIG. 12; FIG. 14 is across-sectional view showing one example of the structure of one deviceregion in the wiring board shown in FIG. 12; and FIG. 15 is across-sectional view showing one example of the structure after solderprecoating in the fabrication of the semiconductor device shown inFIG. 1. FIG. 16 is a plan view showing one example of the structureafter underfill application in the fabrication of the semiconductordevice shown in FIG. 1; FIG. 17 is a cross-sectional view showing oneexample of the structure taken along a line A-A in FIG. 16; and FIG. 18is a cross-sectional view showing one example of the structure afterchip mounting in a flip chip bonding step in the fabrication of thesemiconductor device shown in FIG. 1. FIG. 19 is a cross-sectional viewshowing one example of the structure after pressure bonding of the chipin the flip chip bonding step shown in FIG. 18; and FIG. 20 is across-sectional view showing one example of the structure after ballmounting in the fabrication of the semiconductor device shown in FIG. 1.

1. Provision of Wiring Board (Multi-Piece Wiring Board)

The wiring board according to the present embodiment is, as shown inFIGS. 12 and 13, a multi-piece wiring board (matrix board) 2 t having aplurality of device regions 2 u. Fabrication of a semiconductor deviceby using this multi-piece wiring board 2 t will hereinafter bedescribed. A semiconductor device may however be fabricated by using awiring board which has been divided into each device region 2 u inadvance.

In the fabrication of the semiconductor device according to the presentembodiment, a description will be made referring to drawings showingonly one of the device regions 2 u for convenience sake. It is needlessto say that when the device is manufactured using the multi-piece wiringboard 2 t, a plurality of the device regions 2 u on the multi-piecewiring board 2 t is subjected to a desired treatment in each step.

First, a multi-piece wiring board 2 t is provided. The multi-piecewiring board 2 t has an upper surface 2 a and a lower surface 2 b on theside opposite to the upper surface 2 a. Further, the multi-piece wiringboard 2 t is equipped with a plurality of device regions 2 u (2×4=8device regions 2 u shown here as one example), a cutting site 2 rprovided between the device regions 2 u adjacent to each other among theplurality of device regions 2 u, and a frame portion 2 s provided aroundthe plurality of device regions 2 u in a plan view. The cutting site 2 ris also called “removal site”, “dicing site”, “dicing region”, or thelike.

The cutting site 2 r is in a groove form as shown in FIG. 13. Morespecifically, the cutting site is a groove formed by etching and therebyremoving an electric supply line for forming a plating film on thesurface of each wiring by an electroplating method after forming theplating film. Since the cutting site 2 r is in a groove form, generationof cutting dusts from the solder resist film 2 c during dicing in asingulation step can be reduced. Further, a load to a dicing blade canalso be reduced. Thus, cutting can be performed with an improvedtechnology.

At the extension of each of the cutting sites 2 r on the frame portion 2s shown in FIG. 12, there is an unillustrated dicing mark. During dicingfor singulation, after recognition of the mark, a running line of theblade is found therefrom and then, the blade which is rotating is causedto run to cut the board at the cutting site 2 r.

As shown in FIG. 12, in each of the device regions 2 u, in the openingportion 2 k of the solder resist film 2 c near the center portion of thedevice region, bonding leads 2 m for flip chip connection are arrangedalong each side of the multi-piece wiring board 2 t in two or more rows(here, two rows). Depending on the arrangement of the pads 1 c of thesemiconductor chip 1 shown in FIG. 8, two rows of the bonding leads 2 mare arranged in a zigzag manner. The number of the rows of the bondingleads 2 m may be single (one row).

In each of the device regions 2 u of the multi-piece wiring board 2 taccording to the present embodiment, the bonding leads 2 m are arrangedon an insulation layer 2 d as shown in FIG. 14. This insulation layer 2d is comprised of a prepreg (resin layer) 2 da having a glass cloth(glass fibers) 2 h and a resin layer 2 db not having the glass cloth 2h. The prepreg 2 da has thereon the resin layer 2 db.

Due to such a structure, each of the bonding leads 2 m is in contactwith the resin layer 2 db and is arranged on this resin layer 2 db. Inother words, the bonding leads 2 m are supported by the resin layer 2 dbhaving lower hardness and softer than the prepreg 2 da.

The multi-piece wiring board 2 t has, on the lower surface 2 b thereof,a plurality of lands 2 n electrically connected with the bonding leads 2m on the upper surface 2 a and has, on the lower surface 2 b, a solderresist film 2 g so as to expose each of the lands 2 n.

The multi-piece wiring board 2 t is obtained by overlapping a core layer(prepreg) 2 e, wiring layers 2 i and 2 j on and under the core layer 2e, insulation layers (insulating films) 2 d and 2 f, a wiring layer 2 pconstituting the bonding leads 2 m, and a wiring layer 2 q constitutingthe lands 2 n one after another and bonded by pressing. For example,members such as the core layer 2 e, the wiring layers 2 i and 2 j, theinsulation layers 2 d and 2 f, and the wiring layers 2 p and 2 q aresandwiched between flat plate-like steel plates, followed by pressingthem at a high temperature under a high pressure.

Depending on the position in the device region 2 u, variations tend tooccur in the height of electrodes, particularly, electrodes such as thebonding leads 2 m of the uppermost wiring layer 2 p or electrodes suchas the lands 2 n of the lowermost wiring layer 2 q.

For example, in the bonding leads 2 m formed in the uppermost(outermost) wiring layer 2 p, variations in electrode height may occurdue to contact bonding by pressing.

In consideration of a reduction in connection failures in flip chipconnection due to the above-mentioned variations in the electrodeheight, solder materials 3 are preferably arranged on the surface ofeach of the bonding leads 2 m as shown in FIG. 15. This means that atthe time of flip chip connection, above-mentioned variations inelectrode height can be absorbed by the solder materials 3 arrangedrespectively on the surfaces of the bonding leads 2 m, which leads to areduction in connection failures in the flip chip connection.

When the copper pillar 4 is used as a conductive member for flip chipconnection as shown in the semiconductor chip 1 of FIG. 10, however, thesolder material 3 on the surface of each of the bonding leads 2 m is notalways necessary. In this case, omission of this solder material 3 leadsto a reduction in the cost of the wiring board.

2. Arrangement of Molding Material (Application of Underfill)

As shown in FIGS. 16 and 17, an underfill (molding material) 6 isarranged on the upper surface 2 a of the wiring board 2. This underfill6 is arranged so as to cover a plurality of bonding leads 2 m therewith.The underfill 6 is, for example, an NCF (non-conductive film) and amolding material (adhesive) in film form made of an insulative epoxyresin or the like. Alternatively, an NCP (non-conductive paste) which isa molding material in paste form may be used.

Here, the underfill 6 is arranged on the wiring board 2 prior to flipchip connection. Alternatively, the underfill 6 may be filled betweenthe wiring board 2 and the semiconductor chip 1 after flip, chipconnection.

3. Flip Chip Bonding

As shown in FIG. 18, the semiconductor chip 1 is arranged on the uppersurface 2 a of the wiring board 2. It is arranged while matching theposition of the pads 1 c of the semiconductor chip 1 shown in FIG. 10 tothe position of the bonding leads 2 m of the wiring board 2. Thesemiconductor chip 1 has, as shown in FIGS. 10 and 11, columnar (orprotruding) conductive members (a plurality of copper pillars 4 in thepresent embodiment) formed on each of the pads 1 c.

As shown in FIG. 18, the copper pillars 4 have, on the end surface(surface facing to the bonding leads 2 m) thereof, solder materials 3,respectively.

The semiconductor chip 1 having the pads 1 c provided with the copperpillars 4 having the solder material 3 on the end surfaces thereof isarranged on the upper surface 2 a of the wiring board 2 via the copperpillars 4 so that the main surface 1 a of the semiconductor chip 1 facesto the upper surface 2 a of the wiring board 2.

Then, as shown in FIG. 19, pressure bonding of the chip is conducted. Atthis time, the solder material 3 formed on the end surface of the copperpillar 4 is brought into contact with the bonding lead 2 m of the wiringboard 2 by applying, to the back surface 1 b of the semiconductor chip1, heat and a load (vertical load) F in the thickness direction(perpendicular direction, direction from the upper surface 2 a to thelower surface 2 b of the wiring board 2) of the wiring board 2. Heat isthen applied to a portion to be connected (bonded) between the copperpillar 4 and the bonding lead 2 m to melt the solder material 3 andelectrically connect the copper pillars 4 and the bonding leads 2 m witheach other via the solder material 3.

In the wiring board 2 of the present embodiment, the insulation layer 2d that supports the bonding leads 2 m is the soft resin layer 2 db notcontaining the glass cloth 2 h. When a load is applied to the bondingleads 2 m during flip chip bonding, the resin layer 2 db thereforedeforms and the bonding leads 2 m provided on this resin layer 2 dbsink. Variations in height among the bonding leads 2 m or the conductivemembers (copper pillars 4), if any, therefore does not preventconnection between the copper pillars 4 having a small height and thebonding leads 2 m. Further, since the bonding leads 2 m have, in thelower portion (on the side of the core layer 2 e, on the side of thelower surface 2 b) thereof, the soft resin layer 2 db so that even whena load is applied to the bonding leads 2 m from the copper pillars 4during flip chip bonding, a stress attributable to variations in heightof the electrodes can be absorbed by sinking of the soft resin layer 2db. As a result, a stress to be applied to the semiconductor chip 1 canbe reduced.

This makes it possible to reduce damage to the semiconductor chip 1 andthereby prevent cracks in the semiconductor chip 1 or inconveniencessuch as exfoliation of a surface protective film. In short, damage tothe semiconductor chip 1 during flip chip bonding can be reduced orprevented.

As a result, reliability of the semiconductor device (BGA 7) can beimproved.

When a load is applied during flip chip bonding, the resin layer 2 dbthat supports the bonding leads 2 m sinks to absorb variations in heightamong the copper pillars 4 or the bonding leads 2 m. This makes itpossible to reduce connection failures of the semiconductor chip 1 atthe time of flip chip bonding and thereby improve the connectionreliability of the semiconductor chip 1.

As a result, reliability of the semiconductor device (BGA 7) can beimproved.

In the wiring board 2, the prepreg 2 da has hardness greater than thatof the resin layer 2 db by making the thickness of the prepreg 2 dagreater than that of the resin layer 2 db. As a result, the warpage ofthe board can be reduced. Further, the thickness of the core layer 2 ecan be decreased by thickening the prepreg 2 da of the insulation layer2 d. This leads to a decrease in the total thickness of the wiring board2 and moreover, a decrease in thickness of the semiconductor device (BGA7).

The copper pillars 4 each has, on the end surface thereof, the soldermaterial 3. The solder material 3 melt by heating and absorbs a spacebetween the copper pillar 4 and the bonding lead 2 m formed due tovariations in height among the copper pillars 4 or the bonding leads 2 mwhen the copper pillars 4 are arranged by force.

When not only the copper pillars 4 but also the bonding leads 2 m haveon the surfaces thereof the solder materials 3, variations in heightamong the copper pillars 4 or the bonding leads 2 m can be absorbedfurther and connection failures of the semiconductor chip 1 at the timeof flip chip bonding can be reduced further.

In addition, by using the copper pillars 4 as a conductive member, thecopper pillars 4 can be connected with the pads 1 c collectively in awafer stage. Thus, the conductive member can be connected efficientlywith the pads 1 c.

The copper pillars 4 are columnar conductive members such that they cansecure an electrode height (distance between the semiconductor chip 1and the wiring board 2) in flip chip bonding.

When a load F is added, the underfill 6 is also flattened downwardly bythe semiconductor chip 1 so that the flip chip connection is filled withthe underfill 6 and the underfill 6 flattened to protrude from theperiphery of the semiconductor chip 1 extends over each of the sidesurfaces of the semiconductor chip 1. As a result, the side surfaces ofthe semiconductor chip 1 are each covered with the underfill 6.

Flip chip bonding is completed by the above-mentioned steps.

4. Formation of External Terminal (Ball Mounting)

In an external terminal formation step, as shown in FIG. 20, a pluralityof solder balls 5 is formed on or connected with the plurality of lands2 n on the lower surface 2 b of the wiring board 2. These solder balls 5are also called external terminals, ball-like electrodes, or the like.

The external terminal to be connected with the lands 2 n is not limitedto a ball-like solder material and it may be obtained by coating thesurface of the lands 2 n with a solder material or a plating film(plating layer) formed on the surface of the lands 2 n. In this case,the semiconductor device thus obtained is a LGA (land grid array).

The solder material used for the solder balls 5 is, similar to theabove-mentioned solder material 3, made of a so-called lead-free soldercontaining substantially no lead (Pb). For example, it is made only oftin (Sn) or made of tin-copper-silver (Sn—Cu—Ag).

5. Singulation

A Singulation step is conducted using a dicing blade (not illustrated)which is a rotating cutting blade. For example, singulation into eachBGA 7 is conducted by inserting the blade into the cutting site 2 r fromabove the multi-piece wiring board 2 t as shown in FIG. 12, rotating it,and thereby dicing the wiring board.

The singulation may be achieved not only by dicing with the blade butalso by cutting with a die.

In the above-mentioned manner, fabrication of the BGA 7 shown in FIGS. 1to 3 is completed.

MODIFICATION EXAMPLES

The invention made by the present inventors has been describedspecifically based on the embodiment of the invention. It is howeverneedless to say that the invention is not limited to the above-mentionedembodiment of the invention but can be changed in various ways withoutdeparting from the scope of the invention.

Modification Example 1

FIG. 21 is a plan view showing one example of lead arrangement on theupper surface side of a wiring board to be incorporated in asemiconductor device according to Modification Example 1 of theembodiment.

The structure shown in FIG. 21 shows a modification example of a flipchip bonding type semiconductor device employing multi-pin connection inwhich the arrangement mode of a plurality of bonding leads 2 m on awiring board 2 has been modified.

In the semiconductor device employing multi-pin connection, as isapparent from the semiconductor chip 1 shown in FIG. 8, pads 1 c areoften arranged in a zigzag manner. A plurality of bonding leads 2 mprovided in an opening portion 2 k of a solder resist film 2 c on theside of a wiring board shown in FIG. 21 is arranged in two rows, thatis, an outer peripheral lead group 2 ma and an inner peripheral leadgroup 2 mb.

Further, in the wiring board 2, the inner peripheral lead group 2 mbhas, in a plan view, a plurality of bonding leads 2 mba extending in adirection crossing with (almost perpendicular to) a side 1 d of thesemiconductor chip 1, a plurality of bonding leads 2 mbb extending in adirection crossing with (almost perpendicular to) a side 1 e of thesemiconductor chip 1, and a plurality of bonding leads 2 mbc extendingin a direction perpendicular to neither the side 1 d nor the side 1 e.

This means that the bonding leads 2 m of the inner peripheral lead group2 mb exposed from the frame-like opening portion 2 k of the solderresist film 2 c can be classified into the above-mentioned three groups(bonding leads 2 mba, 2 mbb, and 2 mbc), depending on their extendingdirection. Of these bonding leads of three groups, the bonding leads 2mbc extending in a direction perpendicular to neither the side 1 d northe side 1 e of the semiconductor chip 1 are arranged in the vicinity ofthe corner of the frame-like opening portion 2 k.

This means that among the bonding leads 2 m of the inner periphery leadgroup 2 mb, the bonding lead 2 mbc arranged in the vicinity of thecorner of the opening portion 2 k is likely to contact with a bondinglead 2 mbc located at the end portion (corner) of another lead rowalmost perpendicular to the lead row including the above-mentionedbonding lead 2 mbc. The bonding lead arranged in the vicinity of thecorner is therefore arranged obliquely to the bonding leads 2 m in thevicinity of the center portion of the arrangement. When only the bondinglead 2 mbc at the end position is arranged obliquely, interferencebetween this bonding lead 2 mbc and a bonding lead 2 mbc in the same rowbut adjacent thereto occurs at their inner end portions. A plurality(four leads counted from the end in FIG. 21) of bonding leads 2 mbc inthe vicinity of respective corner portions is arranged obliquely so thatthey radiate out from the center portion of the wiring board 2.

The extending direction of the bonding leads 2 mbc is thereforeperpendicular to neither the side 1 d nor the side 1 e of thesemiconductor chip 1.

Such an arrangement can therefore prevent short-circuit between twobonding leads 2 m adjacent to each other. As a result, multi-pinconnection of a semiconductor device can be achieved.

The bonding leads 2 m of the inner periphery lead group 2 mb each extendalong a direction crossing with (almost perpendicular to) the endportion of an inside solder resist film (inner insulating film) 2 cawhich is a portion of an insulating film covering a portion of thebonding leads 2 m.

This means that all the bonding leads 2 m of the inner peripheral leadgroup 2 mb are arranged on each side of the inner solder resist film 2ca having a substantially square shape so as to be perpendicular to theside (end portion). This makes it possible to make exposure lengths ofthe bonding leads 2 m of the inner periphery lead group 2 mb from theinside solder resist film 2 ca almost equal to each other. This alsoapplies to the bonding leads 2 m of the outer periphery lead group 2 ma.They are arranged so that the exposure lengths of the bonding leads 2 marranged in the opening portion 2 k from the solder resist film 2 c aremade substantially equal to each other.

Even if solder precoats are formed on the bonding leads 2 m, the leadscan be precoated with a substantially equal amount of a solder andtherefore, solder precoats having a substantially equal height can beformed.

As a result, uniform solder wetness can be achieved during flip chipbonding.

Modification Example 2

FIG. 22 is a cross-sectional view showing one example of the structureof a semiconductor device of Modification Example 2 of the embodiment.

The semiconductor device of Modification Example 2 is a chip stack typesemiconductor device. In this semiconductor device, on a semiconductorchip 1 flip chip bonded to a wiring board 2, another semiconductor chip8 is mounted and the semiconductor chip 8 on the upper side iselectrically connected with the wiring board 2 via wires.

The wiring board 2 has, on the side of the lower surface 2 b, aplurality of solder balls 5 as an external terminal. Therefore, thesemiconductor device shown in FIG. 22 is also a BGA 12.

In the BGA 12, for example, the semiconductor chip 1 on the lower sideis a controller chip, while the semiconductor chip 8 on the upper sideis a memory chip. Therefore, it is also a SIP (system in package) typesemiconductor device in which the semiconductor chip 8 on the upper sideis controlled by the semiconductor chip 1 on the lower side. Thesemiconductor chip 1 and the semiconductor chip 8 may however be asemiconductor chip having another function.

The semiconductor chip 8 on the upper side is attached, with a diebonding material 9, onto the back surface 1 b of the semiconductor chip1 on the lower side with the main surface 8 a up. Therefore, the backsurface 1 b of the semiconductor chip 1 on the lower side and the backsurface 8 b of the semiconductor chip 8 on the upper side are bonded toeach other with the die bonding material 9.

A pad 8 c on the main surface 8 a of the semiconductor chip 8 and abonding lead 2 v on the upper surface 2 a of the wiring board 2 areelectrically connected with each other via a wire (conductive member)10. The wire 10 is a gold wire or a copper wire.

The semiconductor chip 1 on the lower side is, similar to the BGA 7 ofthe embodiment, flip chip connected with a plurality of bonding leads 2m of the wiring board 2 via conductive members such as a plurality ofcopper pillars 4. This flip chip connection is protected with anunderfill 6 and the back surface 1 b of the semiconductor chip 1, thesemiconductor chip 8, and the plurality of wires 10 are molded with amolding member 11 made of a molding resin. The molding resin thatconstitutes the molding member 11 is, for example, an epoxy-basedthermosetting resin.

The wiring board 2 of the BGA 12 of Modification Example 2 is similar tothe wiring board 2 of the BGA 7 of the embodiment and an insulationlayer 2 d has thereon a plurality of bonding leads 2 m. This insulationlayer 2 d is comprised of a prepreg (resin layer) 2 da having a glasscloth (glass fibers) 2 h and a resin layer 2 db formed (stacked) on theprepreg 2 da and not having the glass cloth 2 h.

Therefore, the each of bonding leads 2 m contacts with the resin layer 2db and arranged on this resin layer 2 db. This means that the bondingleads 2 m are supported by the resin layer 2 db having lower hardnessand softer than the prepreg 2 da.

The bonding leads 2 m each has therebelow the soft resin layer 2 db sothat similar to the BGA 7 of the embodiment, even when a load is imposedon the bonding leads 2 m from the copper pillars 4 at the time of flipchip bonding, a stress caused by variations in height of electrodes canbe absorbed by sinking of the soft resin layer 2 db, making it possibleto reduce the stress applied to the semiconductor chip 1.

As a result, damage done to the semiconductor chip 1 can be reduced andinconvenience such as formation of cracks in the semiconductor chip 1 orexfoliation of a surface protective film can be prevented. In short,damage of the semiconductor chip 1 in flip chip bonding can be reducedor prevented. This makes it possible to improve the reliability of thesemiconductor device (BGA 12).

The other advantages available by the BGA 12 and fabrication thereof aresimilar to those of the BGA 7 of the embodiment so that an overlappingdescription is omitted.

Modification Example 3

In the above embodiment, a description was made on using, for example, amaterial composed mainly of copper (Cu) as a columnar or protrudingconductive member that electrically connects the semiconductor chip 1with the wiring board 2, but the material is not limited thereto. As amaterial softer than copper (Cu), for example, a material composedmainly of gold (Au) may be used.

When gold (Au) and copper (Cu) are compared, a conductive member made ofgold is itself easily deformable (easily flattened) so that theelectrodes (bonding leads 2 m) of the wiring board 2 are not necessarilysupported by a two-layered insulation layer used as an insulation layerthat supports the electrodes (bonding leads 2 m) of the wiring board 2.In other words, a material (for example, prepreg) harder than the resinlayer not containing the glass cloth (glass fibers) 2 h can be used asan insulation layer that supports the electrodes (bonding leads 2 m) ofthe wiring board 2.

A deformation amount (flattened amount) of the conductive member howeverbecomes large when the height of the conductive members or electrodes(bonding leads) varies greatly. When extreme deformation of theconductive member is not desired, using the wiring board 2 having aninsulation layer with a constitution similar to that of the aboveembodiment is preferred even if the conductive member is made of amaterial composed mainly of gold (Au).

Modification Example 4

FIG. 23 is a cross-sectional view showing one example of the structureof a wiring board to be incorporated in a semiconductor device ofModification Example 4 of the embodiment.

Modification Example 4 shows a modification example of a wiring board tobe incorporated in a semiconductor device. The wiring board 2 shown inFIG. 23 is a so-called two-layered board having two wiring layers. Ithas a wiring layer 2 p on the surface side of a core layer (prepreg) 2 eand a wiring layer 2 q on the back surface side of the core layer 2 e.

Also in the wiring board 2 shown in FIG. 23, a plurality of bondingleads (electrodes) 2 m formed in the wiring layer 2 p have therebelow aresin layer 2 db having hardness lower than that of the core layer 2 ehaving a glass cloth 2 h. Also on the side of the lower surface 2 b, thewiring layer 2 q having therein a plurality of lands (electrodes) 2 nand the core layer 2 e have therebetween a resin layer 2 w havinghardness lower than that of the core layer 2 e.

In the wiring board 2 of Modification Example 4, therefore, aninsulation layer 2 d is comprised of the resin layer 2 db, the corelayer 2 e, and the resin layer 2 w. The bonding leads 2 m are supportedby the soft resin layer (layer not having a glass cloth) 2 db, while thelands 2 n are supported by a soft resin layer (layer not having a glasscloth) 2 w.

Also in the wiring board 2 of Modification Example 4 having atwo-layered wiring structure according to Modification Example 4, thebonding leads 2 m have therebelow the soft resin layer 2 db. Similar tothe BGA 7 of the embodiment, when a load is applied to the resin layer 2db via the bonding leads 2 m at the time of flip chip bonding,deformation of the resin layer 2 db and sinking of the bonding leads 2 moccur. As a result, even if there occur variations in the height ofcopper pillars 4, all the copper pillars 4 can be connected with thebonding leads 2 m. This means that even the copper pillars 4 having lowheight can be connected with the bonding leads 2 m.

As described above, the bonding leads 2 m of the wiring board 2 that areconnected with, among the copper pillars 4, copper pillars having aheight greater than the other copper pillars 4 sink so that formation ofa crack 67 (refer to FIG. 26) in the insulation layer immediately belowthe pads 1 c of the semiconductor chip 1 on which the copper pillars 4having a greater height are formed can be prevented. This makes itpossible to improve the reliability of the BGA 7.

Further, even when a stress is applied to the solder balls 5 of thesemiconductor device (BGA 7) or the like, the stress can be relaxed bythe soft resin layer 2 db and direct propagation of damage to the flipchip connection can be prevented.

In short, even when a stress such as thermal stress is applied to thesolder balls 5, the bonding leads 2 m with which the copper pillars 4are connected have therebelow the soft resin 2 db so that the stress canbe relaxed and absorbed by the deformation of the soft resin layer 2 dbso as to prevent direct propagation of damage to the flip chipconnection or the semiconductor chip 1.

As a result, generation of connection failures of the flip chipconnection can be suppressed.

The other advantages available by the above semiconductor device andfabrication thereof are similar to that of the BGA 7 of the embodimentso that an overlapping description is omitted.

Modification Example 5

With regards to the positional relationship among the resin layers 2 dband 2 fb not containing a glass cloth and the resin layers (prepregs 2da and 2 fa) containing the glass cloth 2 h, the structure of them isnot limited to the stacking structure as described above in theembodiment. As shown in FIG. 24, the resin layers 2 db and 2 fb notcontaining a glass cloth may be provided only immediately below theelectrodes (bonding leads 2 m) with which columnar (or protruding)conductive members (copper pillars 4) are to be connected.

It is however preferred to employ a stacking structure in which layers(resin layers) 2 da, 2 db, 2 fa, and 2 fb have been stacked one afteranother as described in the embodiment when a manufacturing efficiency(number of steps) of the wiring board 2 is taken into consideration.

Modification Example 6

In the above embodiment, BGA has been described as one example of asemiconductor device. The semiconductor device is however not limited toBGA and it may be LGA (land grid array) having, on the surface of a landthereof, a conductive member.

Modification Example 7

Further, the modification examples can be used in combination withoutdeparting from the scope of the technical concept described in the aboveembodiment.

What is claimed is:
 1. A semiconductor device, comprising: a wiringboard having a first insulation layer, a plurality of bonding leadsformed over a first surface of the first insulation layer, and aplurality of lands formed over a second surface of the first insulatinglayer opposite to the first surface, and a semiconductor chip having afirst main surface, a plurality of pads formed over the first mainsurface, and a second main surface opposite to the first main surface,and mounted over the first surface of the wiring board via a pluralityof conductive members such that the first main surface faces the firstsurface of the wiring board; wherein the conductive members areelectrically connected with the bonding leads of the wiring board,respectively, via a plurality of solder materials, wherein the firstinsulation layer has a first resin layer having glass fibers, and asecond resin layer having no glass fibers, and wherein each of thebonding leads contacts with the second resin layer.
 2. The semiconductordevice according to claim 1, wherein the second resin layer has athickness less than that of the first resin layer.
 3. The semiconductordevice according to claim 2, wherein the conductive members each hasmaterial having copper as a main component thereof.
 4. The semiconductordevice according to claim 3, wherein the conductive members are eachcolumnar.
 5. A method of manufacturing a semiconductor device,comprising the steps of: (a) providing a wiring board having a firstinsulation layer, a plurality of bonding leads formed over a firstsurface of the first insulation layer, and a plurality of lands formedover a second surface of the first insulating layer opposite to thefirst surface, wherein the first insulation layer has a first resinlayer having glass fibers, and a second resin layer having no glassfibers, and wherein each of the bonding leads contacts with the secondresin layer; (b) after the step (a), disposing a semiconductor chip overthe first main surface of the wiring board via a plurality of conductivemembers such that a first main surface of the semiconductor chip facesthe first surface of the wiring board, the semiconductor chip having thefirst main surface, a plurality of pads formed over the first mainsurface, and a second main surface opposite to the first main surface;and (c) after the step (b), applying a load to the semiconductor chip ina thickness direction of the wiring board, thereby electricallyconnecting the conductive members with the bonding leads, respectively.6. The method of manufacturing a semiconductor device according to claim5, wherein the second resin layer has a thickness less than that of thefirst resin layer.
 7. The method of manufacturing a semiconductor deviceaccording to claim 6, wherein each of the conductive members has amaterial having copper as a main component thereof.
 8. The method ofmanufacturing a semiconductor device according to claim 7, wherein priorto the step (c), the conductive members each has, on the end surfacethereof, a solder material, while the bonding leads of the wiring boardhave, on the surface thereof, no solder material.
 9. The method ofmanufacturing a semiconductor device according to claim 8, wherein thewiring board is formed by overlapping the first insulation layer, afirst wiring layer constituting the bonding leads, and a second wiringlayer constituting the lands with each other, followed by contactbonding.
 10. The method of manufacturing a semiconductor deviceaccording to claim 9, wherein the conductive members are each columnar.